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<h3 align='center'>Equations</h3>
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********** Mapped Logic **********
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FDCPE_BANK0: FDCPE port map (BANK(0),D(0),N_WR,'0','0',BANK_CE(0));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;BANK_CE(0) <= (A(6) AND A(5) AND A(1) AND A(0) AND NOT A(4) AND N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(7) AND NOT A(3) AND NOT A(2));
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FDCPE_BANK1: FDCPE port map (BANK(1),D(1),N_WR,'0','0',BANK_CE(1));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;BANK_CE(1) <= (A(6) AND A(5) AND A(1) AND A(0) AND NOT A(4) AND N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(7) AND NOT A(3) AND NOT A(2));
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FDCPE_BANK2: FDCPE port map (BANK(2),BANK_D(2),N_WR,'0','0',BANK_CE(2));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;BANK_D(2) <= (JUMPER_COMP_MODE AND D(2));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;BANK_CE(2) <= (A(6) AND A(5) AND A(1) AND A(0) AND NOT A(4) AND N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(7) AND NOT A(3) AND NOT A(2));
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FDCPE_BANK3: FDCPE port map (BANK(3),BANK_D(3),N_WR,'0','0',BANK_CE(3));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;BANK_D(3) <= (JUMPER_COMP_MODE AND D(3));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;BANK_CE(3) <= (A(6) AND A(5) AND A(1) AND A(0) AND NOT A(4) AND N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(7) AND NOT A(3) AND NOT A(2));
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FDCPE_BANK4: FDCPE port map (BANK(4),BANK_D(4),N_WR,'0','0',BANK_CE(4));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;BANK_D(4) <= (JUMPER_COMP_MODE AND D(4));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;BANK_CE(4) <= (A(6) AND A(5) AND A(1) AND A(0) AND NOT A(4) AND N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(7) AND NOT A(3) AND NOT A(2));
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FDCPE_BANK5: FDCPE port map (BANK(5),BANK_D(5),N_WR,'0','0',BANK_CE(5));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;BANK_D(5) <= (JUMPER_COMP_MODE AND D(5));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;BANK_CE(5) <= (A(6) AND A(5) AND A(1) AND A(0) AND NOT A(4) AND N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(7) AND NOT A(3) AND NOT A(2));
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CONMEM <= '0';
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MAPRAM <= '0';
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N_EEPROMCS <= '0';
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N_EEPROMOE <= (N_MREQ AND N_RD);
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N_EEPROMWR <= (N_MREQ AND N_WR AND JUMPER_EEPROM);
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N_IORQEGDE <= '1';
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N_ROMCS <= '1';
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N_SRAMCS <= '0';
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N_SRAMEN <= '0';
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N_SRAMOE <= '0';
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N_SRAMWR <= '0';
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Register Legend:
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FDCPE (Q,D,C,CLR,PRE,CE); 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FTCPE (Q,D,C,CLR,PRE,CE); 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LDCP  (Q,D,G,CLR,PRE); 
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